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Reduced instruction set computing
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141	- - PLAINTIFF’S EXHIBIT Add to Reading List Source URL: www.groklaw.net Language: English - Date: 2007-01-17 17:10:57 Reduced instruction set computing Windows API OS/2 Microsoft Windows Windows NT Computer architecture Software Computing
142	NCE funding for SMART CYBERSECURITY NETWORK (SERENE-RISC) $1.6 million for[removed] Add to Reading List Source URL: www.nce-rce.gc.ca Language: English - Date: 2014-11-24 11:41:44 Computer network security Crime prevention Electronic commerce National security Secure communication Knowledge mobilization ESET Reduced instruction set computing Cyberwarfare Security Computing Computer security
143	25 YEARS AGO: THE FIRST ASYNCHRONOUS MICROPROCESSOR Alain J. Martin Department of Computer Science California Institute of Technology Pasadena, CA 91125, USA Add to Reading List Source URL: authors.library.caltech.edu Language: English - Date: 2014-02-06 14:24:49 Computer hardware Central processing unit Telecommunications engineering Quasi Delay Insensitive Microprocessors Asynchronous circuit CPU design Datapath Reduced instruction set computing Electronic engineering Electrical circuits Electrical engineering
144	Capability Hardware Enhanced RISC Instructions: CHERI Instruction-set architecture Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2014-06-18 09:34:49 Ring MIPS architecture Instruction set 64-bit Hypervisor Reduced instruction set computing Kernel Capability-based security Memory protection Computer architecture Central processing unit Instruction set architectures
145	Bluespec Extensible RISC Implementation: BERI Hardware reference Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2014-07-14 10:37:05 MIPS architecture Instruction set Hardware description language R4000 64-bit Reduced instruction set computing Computer architecture Instruction set architectures Bluespec Inc.
146	Capability Hardware Enhanced RISC Instructions: CHERI Instruction-set architecture Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2014-07-14 10:03:30 MIPS architecture Ring Instruction set 64-bit Hypervisor Reduced instruction set computing Capability-based security Kernel Memory protection Computer architecture Central processing unit Instruction set architectures
147	Mission Research Corporation/ASTER Division Workstations/PC Mission Research Corporation/ASTER Division Add to Reading List Source URL: www.atmet.com Language: English - Date: 2003-12-05 12:46:11 Supercomputers Parallel computing Control Data Corporation Cray-1 Cray VAX CDC National Center for Atmospheric Research Reduced instruction set computing Computing Classes of computers Computer architecture
148	DOC Document Add to Reading List Source URL: www.reinventingschools.org Language: English - Date: 2012-12-11 14:13:57 Social media Online community NeXT Technology Reduced instruction set computing Computing
149	MIPS Assembly Language Guide MIPS is an example of a Reduced Instruction Set Computer (RISC) which was designed for easy instruction pipelining. MIPS has a “Load/Store” architecture since all instructions (other than Add to Reading List Source URL: www.cs.uni.edu Language: English - Date: 2008-03-04 08:20:27 Instruction set architectures MIPS architecture Calling convention SPIM Processor register 64-bit Subroutine Computer architecture Computing Computer programming
150	NISTIR 7950 Examination of the Impact of Fingerprint Spatial Area Loss on Matcher Performance in Various Mobile Identification Scenarios Add to Reading List Source URL: nvlpubs.nist.gov Language: English - Date: 2014-03-24 11:59:56 Fingerprints Surveillance Information Fingers Human anatomy Reduced instruction set computing Device fingerprint Biometrics Security Identification

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